A phase change element (phase change element: abbreviated as “PCE”) used in a cell of a phase change memory includes a phase change material such as chalcogenide (Ge2Sb2Te5, for example), and a resistance value of the phase change element can be arbitrarily varied by controlling a current, a voltage, and a pulse shape of the voltage at a time of writing. In a binary memory element, in general, writing or a written state in which a cell assumes a high resistance is referred to as “reset”, and data “0” is assigned to the state of “reset”. On the contrary, writing or written state in which the cell assumes a low resistance is referred to as “set”, and data “1” is assigned to the state of “set”. When a PCE is heated to a temperature of a melting point or more and is then cooled at a comparatively fast speed, the PCE becomes amorphous (reset state) with a high resistance. When the PCE is held for a comparatively long period of time at a temperature not less than a crystallization temperature but not more than the melting point and is cooled at a comparatively slow speed, for example, the PCE has a crystallization state (set state) with a low resistance.
A resistance ratio between the set state and the reset state is large in the PCE. Thus, the PCE has an advantage that data is easier to read than other resistance-change type memories.
However, there is pointed out a problem of the PCE that a cell resistance value (transient resistance value) for several 10 ns from immediately after reset writing is excessively reduced as compared with a cell resistance value (steady-state resistance value) after a subsequent elapse of time (refer to Non-patent Document 1, for example). FIG. 5 of Non-patent Document 1 shows that a threshold VT has risen from about 0.5V to 0.7V in initial 30 ns after a reset pulse, and then saturates. FIG. 10 of Non-patent Document 1 shows extrapolation curves from immediately after reset writing to 100 ns or less, based on the result of measurement of a resistance R and VT-R correlation.
For this reason, when information (data) is read from a cell at a comparatively fast timing of several 10 ns after completion of writing of data into the cell in a verify operation, a transient resistance value which is extremely lower than a steady-state resistance value may be read, wherein in the verify operation, after data has been written into a cell, the data is read from the cell and pass/fail status is determined by comparing the readout data with write data.
Writing of data into a PCE is conducted by Joule heat generated by application of current. Thus, in a time range of several 10 ns immediately after the writing, a temperature of the PCE may not be sufficiently reduced to a range in which the data can be read. This may cause resistance values of the PCE immediately after the writing in both set and reset states to be unstable.
Patent Document 1 discloses a configuration including a read data latch which holds read data from a phase change memory cell and latches write data received from an outside, a write data latch which holds write data in a memory cell during a predetermined cycle until a start of writing, a transfer switch that controls presence or absence of transfer of an output of the read data latch to the write data latch, a comparison circuit which determines whether or not the data held in the write data latch matches the data in the read data latch, and a write flag latch which s h latches an output of the comparison circuit. Only when a write request is pending and a result of comparison of the comparison circuit indicates a mismatch, writing is performed. The writing is thereby performed only to a necessary bit. This configuration allows hiding of a comparatively long write time for a phase change memory to execute random writing to the phase change memory.
Patent Document 2 discloses a method of operating a phase change memory device including a step of programming a write data block including N number of unit program blocks in response to a request for a programming operation, a step of suspending the programming operation in response to a request for a read operation after M number of unit program blocks (M being smaller than N) have been programmed, a step of performing the requested read operation, and a step of resuming programming of the write data block and programming (N−M) number of remaining unit program blocks.
Patent Document 3 discloses a highly integrated and a high-speed non-volatile memory which stabilizes an operation of a phase change memory for a short operation cycle time. In this memory, a latch is provided in a write driver WD. A change to a high-resistance state of a phase change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state of the phase change element is performed after a pre-charge command has been received and concurrently with deactivation of a pre-charge signal. With this arrangement, a write time to a memory cell in which phase change resistance is changed to a low-resistance state, and a period from a writing operation for changing the phase-change resistance, to a high-resistance state to a reading operation from the memory cell can be lengthened without extending the column cycle time, so that the stable writing operation is achieved.
Patent Document 4 discloses a semiconductor memory device including detection means for executing a writing process to memory cells in an address region, executing a block verification process for collectively performing verify operations of a plurality of addresses, repeating the block verification process and the writing process, and detecting whether or not a memory cell which has not been written yet is included in each address. In at least a part of the block verification process, at least a portion of addresses which has been determined not to include a memory cell that has not been written yet in a verification process executed one or more times before the block verification process is excluded. With this arrangement, the block verification process is executed. A period of time required for the block verification process can be thereby reduced and high-speed buffer writing can be performed. Patent Documents 1 to 4, however, never disclose recognition of the problems pointed out by Non-patent Document 1 and means for solving the problems.
Patent Document 1:
    JP Patent Kokai Publication No. JP2008-159178A which corresponds to U.S. Pat. No. 7,813,178B2Patent Document 2:    JP Patent Kokai Publication No. JP2007-250171APatent Document 3:    JP Patent Kokai Publication No. JP2005-158199A which corresponds to U.S. Pat. No. 7,154,788B2, U.S. Pat. No. 7,257,034B2 and U.S. Pat. No. 7,613,038B2Patent Document 4:    JP Patent Kokai Publication No. JP2007-188552A which corresponds to U.S. Pat. No. 7,545,683B2Non-patent Document 1:    D. Ielmini, A. L. Lacaita, D. Mantegazza, F. Pellizzer, and A. Pirovano “Assessment of threshold switching dynamics in phase-change chalcogenide memories”, Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International Volume, Issue, 5-5 December 2005 Page(s): 877-880